The present application generally relates to automatic power management in a parallel computing system that includes a plurality of processors. More particularly, the present application relates to automatically controlling power dissipation of a parallel computing system via commands generated from a host computing device.
Certain computing systems and super computing systems, for example BLUE GENE® (registered trademark of International Business Machines, Incorporated), have a single global clock signal, also known as a system clock signal, that controls all processors in the systems. Such a single system clock signal simplifies processor-to-processor communication circuitry. However, the simplified processor-to-processor communication circuitry leads to an additional requirement: if the frequencies of the processor-to-processor communication circuitry are changed, then the frequency change needs to be carefully orchestrated across all processors in these systems, to maintain processor-to-processor communication integrity.
Typical power saving mechanisms developed for computing systems only act locally, in the sense that they only affect individual processors in the computing system and are based on local temperature or workload conditions. Such mechanisms do not generally take into account global parameters (e.g., temperature, time varying electricity cost, etc.) of a room or data center where the computing system is operated. A parallel computing system (e.g., IBM® BLUE GENE®, Cray® XE™ supercomputers, etc.), however, includes up to thousands of processors (e.g., IBM® PowerPC®, Intel® Core™, etc.). These thousands of processors in the parallel computing system consume so much energy (e.g., 30 to 100 kW power consumption per one thousand operating processors in the parallel computing system) that developers of the parallel computing system need to consider the global parameters and limitations of the room or data center.
The active or switching power dissipated by an electronic circuit (e.g., a processor, memory device, etc.) can be described as P=½×C×Vdd2×f×a, where P is the power dissipation of the electronic circuit, C is a capacitance being switched in the electronic circuit, Vdd is a power supply voltage to the electronic circuit, f is a clock frequency (e.g. of the fastest clock on the chip, e.g., a processor clock) of the electronic circuit, and “a” is a switching activity factor of the electronic circuit, which is the fraction of clock cycles at frequency “f” that the circuit is actually active and switching. For the total switching power dissipation of a processor, the contribution of each sub-circuit has to be summed. For the total switching power dissipation of a parallel computing system, the contribution of each processor has to be summed, along with the contributions of non-processor chips (e.g., memory devices, interconnects, etc.).